Intel Chooses Averna for Testing DOCSIS 3.1 Chipsets

Averna’s DOCSIS 3.1 Protocol Analyzer Accelerates Design Validation and Certification

Montreal, Canada – October 6, 2015 – Averna, an industry-leading developer of test solutions and services for communications and electronics device-makers worldwide, announced today that Intel has selected Averna’s DP-1000 DOCSIS® Protocol Analyzer to test its DOCSIS 3.1 chipset prior to final certification.

The DP-1000 captures and filters MAC-layer data in real-time to verify RF parameters, validate MAC-level communication, troubleshoot interoperability issues, and improve performance.

Developed with major industry players and designed for both DOCSIS 3.0 and DOCSIS 3.1, the DP-1000 provides users with state-of-the-art tools for analyzing, debugging, maintaining and monitoring local networks and Internet connections. Multiple system operators (MSOs), chipset manufacturers, product developers and certifications bodies use it to quickly find and correct trouble spots in order to maintain the highest quality of service possible.

Optimized for real-time signal processing with FPGA technology, the DP-1000 analyzes up to 32×8 single or bonded US/DS channels (DOCSIS 3.0) and 2×1 OFDM US/DS channels (DOCSIS 3.1), and includes numerous channel-filtering, demodulation, triggering, display, and upgrade features.

“Intel was seeking a solution to test its new chipset for D3.1 as well as D3.0, validate CableLabs® specifications for the MAC-layer and parts of the PHY-layer, as well as evaluate CMTS interoperability,” said Alex Pelland, Director of Broadband Test Strategy at Averna. “Our DP-1000 DOCSIS Protocol Analyzer was a perfect fit for these requirements. Since DOCSIS 3.1 will enable a new generation of sophisticated products and cable services, broadband product developers like Intel will benefit from the DP-1000’s ability to accelerate the important validation and certification phases.”

DP-1000 Highlights

Supports both DOCSIS 3.0, 3.1, and some mixed mode.
Input frequency range 100 MHz–1.8 GHz DS, 5 MHz –200 MHz US
Acquisition cards of 200 MHz bandwidth each
Contained in a single, 19-inch (48 cm), 4U rack for minimal footprint (60 lbs/27 kg)
FPGA-based architecture is highly flexible, configurable, upgradable and extendable
Many channel-filtering, demodulation & decoding, triggering, display, and upgrade features
Optional DOCSIS VSA enables RF spectrum and synchronized signal analysis for both US and DS, including burst, constellation, SNR, MER, EVM and power level

DP-1000 in the News

Averna received the 2015 Global DOCSIS Cable Networks New Product Innovation Award from Frost & Sullivan for pioneering its DP-1000 DOCSIS Protocol Analyzer solution.

Click to Tweet: From @Avernatech: Intel Chooses Averna for Testing #DOCSIS 3.1 Chipsets, www.averna.com

About Averna

As the leading Test Engineering company in the world, Averna is a strategic partner for electronic and communication product developers, helping them achieve higher product quality, faster time to market, and greater value from their test systems. Founded in 1999, Averna offers specialized expertise and innovative test solutions that deliver substantial financial, technical and brand benefits for hundreds of clients in the aerospace, automotive, consumer electronics, defense, life sciences, telecom and transportation industries. Averna has offices around the world, numerous industry certifications such as ISO, CSIA, and ITAR registration, and is partnered with National Instruments, Keysight Technologies, and JOT Automation. www.averna.com

© Copyright 2015 Averna. All rights reserved. Information subject to change without notice. Averna is a trademark of Averna Technologies Inc. CableLabs and DOCSIS are trademarks of Cable Television Laboratories, Inc. Other product and company names listed are trademarks of their respective companies.